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Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi ! #embedded #HDL #RTL #Verilog #VHDL #HLS https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/ethernet_top.c
Hi, I’m Max! I’m an engineer passionate about both hardware & software. I'm a Principal Engineer at Intel helping to shape the future of hardware, and I lead the open-source ROHD project, making hardware development more accessible and fun.
I enjoy working on personal projects (especially with Dart), snowboarding 
, gaming 
, and exploring new tech.
Excited to connect with folks in open-source, hardware, and beyond! 
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Learn PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro covers #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS
https://www.youtube.com/watch?v=wWdvuAQXeS0
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WHY! GAH! 
In the mood for the littlest bit of #FPGA #GameDev? 
Check out this pico-ice based #pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/pong_top.c
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@LilahTovMoon AFAICT this option.does not exist in #Germany, because here #Amazon mixes between #HDL and pseudo-freelancers working for sub-sub-subcontractors.
Lispy gopher climate #podcast coming up in two hours (at 000UTC Wednesday, aka Tuesday night for many).
https://anonradio.net/
Building a date prompt from my conference talk #mcclim #commonLisp
Hooking that to an #emacs #hook, my workaround.
Drawing inspiration from @kickingvegas' #casual (#emacsconf)
#lispCurse and @fosskers' transducers ; the little known counter-narrative evolution of the #lisp curse
Lisp Machine Revolution @amszmidt looking for #HDL + lisp collaborators.
#eevel mode ?
anonradio.net// aNONradio // – [LIVE]: Language Soup w/ DJ Supersalad with handyc
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Come on over to the Discord channel if you want to join the conversation about this fun work https://discord.gg/vBUtmBZcxC #FPGA #raspberrypi #pico-ice #PipelineC #HDL #Verilog #VHDL
DiscordJoin the tinyVision.ai Discord Server!Check out the tinyVision.ai community on Discord - hang out with 702 other members and enjoy free voice and text chat.
Have been super pleased with the #ice40 #FPGA and #raspberrypi board that https://pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice #HDL #Verilog #VHDL #hardware #embedded
pico-ice.tinyvision.aipico-ice: Main Page
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often I see RTL designers use non-blocking assignment everywhere, with or without a real need for it, unnecessary complicating the behavior, including resetting logic, utilizing excessive memory, and introducing unnecessary latencies
I guess they were once taught about propagation delays and pipelining as a measure of managing them, and since then try to make ad-hoc pipeline out of everything
still I find it lame and prefer to make everything combinational if possible, and only introduce extra memory if synthesis fails for given timing constraints
#HDL #VHDL #SystemVerilog #Verilog
I guess they were once taught about propagation delays and pipelining as a measure of managing them, and since then try to make ad-hoc pipeline out of everything
still I find it lame and prefer to make everything combinational if possible, and only introduce extra memory if synthesis fails for given timing constraints
#HDL #VHDL #SystemVerilog #Verilog
stereophonic.spaceStereophonica
for #SystemRDL and similar languages there are (synthesisable) register block generators, having #AXI or AXI Lite on one end and a bunch on signals corresponding to the fields on another
similar generated blocks for parsing and forming AXI Stream should be a thing as well, turning an octet stream into a structure together with a validity and no-longer-needed signals, or vice versa
#HDL #VHDL #SystemVerilog #Verilog #HLS
similar generated blocks for parsing and forming AXI Stream should be a thing as well, turning an octet stream into a structure together with a validity and no-longer-needed signals, or vice versa
#HDL #VHDL #SystemVerilog #Verilog #HLS
stereophonic.spaceStereophonica
Just published in the October issue of IEEE #TCAD: "WAVING Goodbye to Manual Waveform Analysis in HDL Design with WAL".
PDF (open access): https://ieeexplore.ieee.org/document/10496480
WAL: https://wal-lang.org 
GitHub: https://github.com/ics-jku/wal
