Right now, the "official" RISC-V reference implementation, Rocket, is still ASIC-optimized. FPGA-based RISC-V cores tend to be home-grown things these days.
You can still synthesize Rocket on an FPGA, but because it's optimized for ASICs, it needs a rather large FPGA to do so, since it's investing individual LUTs to things that can be only a few transistors in an ASIC.
@vertigo What I mean is that the current state of affairs makes every industrially-made CPU suspectful. Especially those made in countries with governments known for spying on citizens wholesale, who attempted to build the Clipper chip in the past.
I'm wondering how far we can go building these systems really from scratch. We still depend on Xilinx or Altera/Intel at some point anyway.
I'm curious about your point of view on these matters.
@bob @jjg @cstanhope @h Wasn't there someone looking to make 10um or 8um feature-sized semiconductors using garage-accessible equipment not long ago? If so, and once you're familiar with the characteristics of the transistors at those sizes, you can definitely at least make a Z80 or 6502 equivalent CPU.
My motivation is threefold:
1. Learn how to actually build stuff with FPGA and start with open tools of at all possible
2. Design a module for RAIN that can be used to provide application-specific logic, acceleration and other experimental stuff along side the traditional processor modules
@jjg This is amazing news! Tangentialy related: I'm trying to see how hard it would be to build a REBOL interpreter in a common assembler (similar to the way Forths are often built). The main reason is I would like my work-in-progress hypermedia engine to eventually run on your free computer architecture and on @vertigo's as well.
@cstanhope I had expected to write a Lisp/Forth/Rebol-like language on top of Go, so I could take advantage of its magnificent cross-compiler, but seeing that RISC-V is not one of Go's target architectures (mainly amd64 and ARM were of interest until now) that it's making me rethink the whole language layer thing. @bob @vertigo @jjg
@jjg Please cc me when you post, I'm definitely interested. Also moving to start a blog of my own soon. I have enough bits working already that it makes sense to start some new interesting discussions. I don't mean to coordinate too much, but discussing some loose interfaces to ensure that my stuff works on your (jjjg's and vertigo') gear would be important to me personally. And hopefully I'll be able to explain why and how.
Soon! @cstanhope @bob @vertigo
@jjg I think it may be a good idea to consider it. It certainly won't make you poorer, and I think you will appreciate the simplicity of it, as a kind of better Lisp and better Forth rolled into one. Vertigo certainly convinced me. It's possible that I may also borrow some good ideas from @akkartik's language if strict compatibility with standard REBOL is not considered necessary, but in a nutshell that's the general direction I think I'm going now.
@cstanhope @bob @vertigo
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