Nerdworld problems - Verilog edition Show more
TIL Verilog 2001 doesn't allow you to have 0 in a replication operation. So if you have a module parameter that is 0, e.g. WIDTH, then this will not produce a two bit wide vector:
Tiny bummer. :/
Of course, it also doesn't produce an error in simulation. Instead it just produces nonsense that you have to figure out for yourself. Thanks for nothing, expensive tools.
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